Frequency-Modulated Continuous-Wave Radar

Next high-level section: PCB Design

Most of the steps in this derivation are identical to the derivation for the well-known Friis transmission formula.

Start by imagining that our transmission antenna is isotropic. The power density at some remote distance $R$ is given by

where $P_{\mathrm{T}}$ is the transmitted power. The $4\pi R^{2}$ comes from the fact that the isotropic antenna by definition radiates power equally in all directions and therefore the power density at some distance is inversely related to the surface area of the sphere centered at the transmission antenna. Now we replace the isotropic antenna with an antenna with gain $G_{\mathrm{T}}$ in the direction of $R$ and the equation becomes

At this distance, $R$, the transmitted signal reflects off a remote object. The total reflected power is

where $\sigma$ is the cross-sectional area of the remote object. This is a bit of a simplification, since the total reflected power will be dependent on several other factors such as the material properties of the remote object and its shape. We lump all these additional factors into the cross-sectional area, which therefore generally is not exactly equal to the object's actual cross-sectional area.

We now imagine the remote object simply as a remote isotropic antenna with transmission power given by the reflected power shown above. And we use the same method as the first step to find the power density available at the reception antenna:

To find the actual received power, we multiply the power density by the reception antenna's effective aperture and efficiency:

This is the final result. We could equivalently rearrange our equation in terms of the distance,

In our case the transmission and reception antennas are identical, so the equation simplifies to

Next high-level section: Receiver

The ADF4158 frequency synthesizer is based on a fractional-N phase-locked loop (PLL) design. The device is highly configurable, which can be viewed in the datasheet. Chapter 13 of the Art of Electronics (3d ed.) (AoE) provides an excellent description of how a PLL works. I explain the relevant points here. The frequency synthesizer consists of a phase detector and VCO (our VCO is an external component). Figure 12 shows a block diagram of the synthesizer (note that this diagram has been adapted from AoE).

The phase detector, as the name suggests, outputs a voltage signal which corresponds to the difference in phase between two input frequencies. The VCO generates a frequency that is proportional to an input voltage. (Disregard the frequency divider blocks for a minute. We'll get back to them.) $f_{\mathrm{REF}}$ is a reference frequency. In our case this is a $40\text{\,}\mathrm{M}\mathrm{H}\mathrm{z}$ clock frequency. Imagine that the rising edge of $f_{\mathrm{REF}}$ occurs before the rising edge of $f_{\mathrm{VCO}}$. In response, the phase detector increases it's output voltage corresponding to the duration of time that $f_{\mathrm{REF}}$ leads $f_{\mathrm{VCO}}$. This causes the VCO output frequency to increase accordingly and causes the next edge of the VCO output to occur sooner than the previous one. So, the phase gap diminishes or reverses. The opposite occurs when $f_{\mathrm{REF}}$ lags behind $f_{\mathrm{VCO}}$. The phase detector is detecting differences in phase, not frequency. However, any differences in frequency will lead to phase differences, and thus the phase detector will cause the frequency and phase of $f_{\mathrm{VCO}}$ to converge to that of $f_{\mathrm{REF}}$.

All we've done so far is take $f_{\mathrm{REF}}$ and generate another signal $f_{\mathrm{VCO}}$ with identical frequency and phase, which isn't particularly useful. This is where the frequency dividers come in. The R divider takes $f_{\mathrm{REF}}$ and outputs a frequency $f_{\mathrm{REF}}/r$. The N divider does the same thing for $f_{\mathrm{VCO}}$. So, what we're doing is setting

By setting $n$ much larger than $r$, we can generate an output frequency that is much higher than the reference frequency. Figure 12 isn't completely accurate. What we've shown is an integer-N frequency synthesizer, whereas the device we're using is a fractional-N frequency synthesizer. The practical difference is that our value of $n$ can be non-integral, which allows finer-grained control of the output frequency.

Next high-level section: Receiver

A resistive splitter is a circuit that splits the power at its input between two outputs. The splitter used in this design splits the power evenly between both outputs, though there are splitters designed for uneven splits. Because the splitter is resistive, it loses half of the input power to heat. This leaves $6\text{\,}\mathrm{d}\mathrm{B}$ below the input power at each output. A common alternative to a resistive splitter is a Wilkinson power divider. The power divider has the benefit of being lossless. That is, the power at each output will be $3\text{\,}\mathrm{d}\mathrm{B}$ below the input. However, the price paid for this improved efficiency is bandwidth. The reason for this is that each branch of a Wilkinson divider is set to a quarter wavelength. Because wavelength is inversely related to frequency, this will only be suitable for a limited frequency band. The power divider, by contrast, just requires 3 resistors and so its bandwidth is defined by the parasitic values of these resistors.

Our requirements for the splitter or divider are not very demanding. The bandwidth is limited and the power available to the splitter is enough for each output even with the loss. Also, the power is low enough that the heat dissipation doesn't pose a problem. Therefore, using either of these devices would have worked fine. I've opted to use the splitter since this allows us to use one less attenuator and therefore costs marginally less.

Next high-level section: Receiver

An attenuator is a relatively simple circuit that produces an output power which is a desired fraction of the input power. Although I've used an IC for tighter tolerance and better frequency characteristics, the equivalent schematic is very simple and shown in Figure 13. There are several different resistor configurations to create an attenuator. The Pi attenuator shown below is just one of them.

We can get an even more complete picture if we explicitly show the source and load resistance. This is shown in Figure 14.

Typically, our source and load impedance will be matched to the characteristic impedance: $R_{\mathrm{S}}=R_{\mathrm{L}}=Z_{0}$. Now we need to choose $R_{1}$ and $R_{2}$ for the desired attenuation, but subject to the constraint that the attenuator does not present an impedance mismatch and cause signal reflections. To satisfy this, we constrain the Thévenin network of resistors to the right of $R_{\mathrm{S}}$ to be equal to the characteristic impedance, $Z_{0}$. It is then a simple matter of algebra to show that this sets the relation between $R_{1}$, $R_{2}$ and $Z_{0}$ to be

To find the attenuation, we need to find the voltage transfer function for the attenuator, $V_{\mathrm{out}_{\mathrm{a}}}/V_{\mathrm{in}_{\mathrm{a}}}$. The attenuation will be the decibel value of the inverse of this ratio:

Finally, we can rearrange our equations to represent the attenuator resistors in terms of the voltage transfer function, $x$, and decibel attenuation, $A$, which are more useful:

Next high-level section: Receiver

A coupler is a device that is able to share the power of a signal at an input port between two output ports. Its schematic depiction is shown in Figure 15.

The signal enters at the input port and most of the energy passes through to the transmitted port. Some input energy, however, exits through the coupled port where the amount is given by the coupling factor. See the relevent RF simulation section for more information on how this works. The insertion loss describes how much of the input power makes it to the transmitted port.

The equations for coupling factor and insertion loss are

The coupler we use has a coupling factor of $-$20\text{\,}\mathrm{d}\mathrm{B}$$ and the power amplifier has an output power of $26\text{\,}\mathrm{d}\mathrm{B}\mathrm{m}$ which gives a coupled power of $6\text{\,}\mathrm{d}\mathrm{B}\mathrm{m}$. The coupler's insertion loss is $0.17\text{\,}\mathrm{d}\mathrm{B}$, which means the transmitted power is nearly the same as the input power, and so we'll take it to be $26\text{\,}\mathrm{d}\mathrm{B}\mathrm{m}$.

Another important quantity for a coupler (it is often one of the most important criteria for assessing the quality of a coupler) is the coupler's directivity. It is given mathematically as

The directivity represents the ratio of the power available at the isolated port to the power available at the coupled port. Ideally, no power makes it to the isolated port, which would make the directivity infinite. Directivity permits the coupler to differentiate between forward and reverse signals. Having a high directivity is crucial for many devices (e.g. VNAs) but is less critical in our application. Indeed, the directional coupler used here was designed for simplicity of fabrication and to consume minimal board area, but exhibits poor directivity.

Next high-level section: Receiver

The power amplifier does exactly what its name suggests: it increases the signal power for transmission. This design uses a SE5004L power amplifier. The most important metrics for us to consider when choosing a power amplifier are the gain and $1\text{\,}\mathrm{d}\mathrm{B}$ compression point. We also, of course, need to ensure the operating frequency range accommodates our signal frequency. This power amplifier has a small signal gain of $32\text{\,}\mathrm{d}\mathrm{B}$ and an output compression point of $34\text{\,}\mathrm{d}\mathrm{B}\mathrm{m}$. Its input power is $-$6\text{\,}\mathrm{d}\mathrm{B}\mathrm{m}$$, which puts the output power at $26\text{\,}\mathrm{d}\mathrm{B}\mathrm{m}$, well below the compression point. We could increase the max range somewhat by increasing the power amplification (see the range section). However, this would also increase the minimum range, which isn't a great tradeoff. Moreover, increasing the power amplification would increase the power consumption of the board and heat dissipation, which we would need to mitigate. Finally, there are easier ways of increasing the max range, for instance by changing the intermediate frequency (IF) amplifier frequency response.

The radar's dynamic range is the ratio between the maximum signal the receiver can process and its noise floor. See those sections to see how the dynamic range was computed. We find that the theoretical dynamic range is equal to about $102\text{\,}\mathrm{d}\mathrm{B}$ and roughly constant across the signal bandwidth of interest. This is shown in Figure 17.

As discussed in the range section, the actual noise floor is higher than the theoretical value. A plot of the noise floor up to the decimated Nyquist frequency is shown in Figure 18.

Next high-level section: Differential Amplifier

A multiplicative mixer is a device that multiplies two input signals. Many mixers (including the one used in this design) are based on a Gilbert cell, whose schematic is shown in Figure 22.

The lower differential pair sets the gain of each of the top two differential pairs. For instance, if $V_{\mathit{LO}}$ is made positive there will be more total emitter current for the left differential pair than for the right differential pair. The top input, $V_{\mathrm{in}}$, is cross connected between the top transistors. That is, $V_{\mathrm{in}+}$ is connected to the base of two transistors whose collectors are tied to different polarities of $V_{\mathrm{out}}$.

To understand the operation, start by setting $V_{\mathit{LO}}=0$. It doesn't matter what we set $V_{\mathrm{in}}$ to, $V_{\mathrm{out}}$ will always be 0. For instance, if $V_{\mathrm{in}}>0$, $Q_{1}$'s collector current will be greater than that of $Q_{2}$, but $Q_{4}$'s collector current will exceed that of $Q_{3}$ by the exact same amount (remember $V_{\mathit{LO}}=0$ so the differential gain of each amplifier is identical). Since the voltage drop across the leftmost $R_{\mathrm{C}}$ is determined by the combined currents to $Q_{1}$'s and $Q_{3}$'s collectors and the drop across the rightmost $R_{\mathrm{C}}$ is determined by the combined currents to $Q_{2}$'s and $Q_{4}$'s collectors, the voltage drops will be identical. When $V_{\mathrm{in}}=0$ the collector current for each transistor within a differential pair will be the same. So, even if we change $V_{\mathit{LO}}$ to change the total emitter current for each upper differential pair, the output voltage will still be 0.

If we set $V_{\mathit{LO}}>0$, this increases the total emitter current for the left differential pair compared to the right differential pair. Then, $V_{\mathrm{in}}>0$ will increase $Q_{1}$'s and $Q_{4}$'s collector currents and decrease those for $Q_{2}$ and $Q_{3}$, but it will change $Q_{1}$'s and $Q_{2}$'s collector currents more than it changes the collector currents for $Q_{3}$ and $Q_{4}$. So the net effect is that $V_{\mathrm{out}}>0$. We can continue to analyze the circuit using the same procedure to find that the circuit's voltage transfer function is given by

where $g$ is some gain factor.

The differential amplifier's input circuitry is worth discussing because it affects the amplifier's frequency response. There are three logical parts to this, separated by dashed lines in Figure 23. The pullup resistors at the mixer output set the DC bias point of the output to $5\text{\,}\mathrm{V}$. This is followed by an LC lowpass filter. And then the differential amplifier acts as a second-order active bandpass filter, with roughly $23.5\text{\,}\mathrm{d}\mathrm{B}$ of gain (though it varies with frequency). The DC blocking capacitors in the active filter serve an additional purpose, which is to allow the differential amplifier's input voltages to float down to the acceptable input range. This is critical because the $5\text{\,}\mathrm{V}$ bias point would be too high for the amplifier, which has a supply voltage of $3.3\text{\,}\mathrm{V}$.

The frequency response of this circuit is shown in Figure 24.

This design uses an LTC2292 ADC.

The heart of this project is its use of an FPGA, which offers unique performance attributes and design challenges. The FPGA serves two purposes: it performs data processing, and it acts as an interface to configure other ICs on the PCB. An FPGA can implement any digital logic circuit, within resource limitations, which gives us a tremendous amount of flexibility in regard to how we process the raw data and how to interact with and configure the other PCB ICs. The benefit of using the FPGA rather than software on the host PC for data processing is that it can run these algorithms faster than traditional software, and it also allows us to ease the burden on the USB data link between the radar and host PC. In regard to the second point, the bandwidth between the radar and host PC is limited by the USB 2.0 High Speed data transfer speeds of $480\text{\,}\mathrm{M}\mathrm{b}\mathrm{p}\mathrm{s}$, which is an upper bound (the practical speed is lower, typically about $320\text{\,}\mathrm{M}\mathrm{b}\mathrm{p}\mathrm{s}$). By using the memory facilities of the FPGA as a buffer, we can send the raw data directly to the host PC and process and plot it in real time. However, if our data link was slower (e.g., our host computer only supported a USB 1.0 interface), we could ease the burden on the data link by performing the processing directly on the FPGA. This works because the FIR decimation filter only keeps 1 sample out of every 20 inputs.

This design uses an XC7A15T FPGA from Xilinx, which is a low-cost FPGA but is nonetheless sufficient for our needs. One additional benefit of using this FPGA is that it is pin-compatible with a number of higher resource count variants. Consequently, if our data processing needs expand in the future, we can use one of those variants as a drop-in replacement without otherwise altering the PCB.

The FT2232H is a USB interface chip that permits 2-way communication with the FPGA and enables us to load a bitstream onto the FPGA. The attached EEPROM chip is required to use the FT2232H in its FT245 synchronous FIFO mode, which allows the full $480\text{\,}\mathrm{M}\mathrm{b}\mathrm{p}\mathrm{s}$ data transfer speed.

Next high-level section: FPGA Gateware

A simple implementation of a voltage regulator is shown in Figure 29. This has been adapted from AoE.

The operation of this circuit is very simple. The non-inverting input of the opamp is set by a current source supplying a zener diode. The current source provides a constant current over changes in the input voltage, so the voltage across the zener remains fixed at the desired reference. The inverting input is tied to a voltage divider output from the output voltage. The resistors are chosen to provide a desired output voltage for the reference voltage. Mathematically,

Finally, a darlington pair provides current amplification. So, for instance, even if our opamp could supply only about $1\text{\,}\mathrm{m}\mathrm{A}$ of current, darlington pairs often have current amplification on the order of $1000$ or more, so this regulator would be able to supply $1\text{\,}\mathrm{A}$ of current to a downstream device.

It's important to consider $Q_{2}$'s power dissipation. Specifically, it will dissipate

For large voltage drops and large currents, this can amount to a significant amount of power, which the transistor must be designed to handle. Moreover, this is wasted power, which is the reason for the use of LDO regulators in the radar.

It's also worth noting that this implementation has some drawbacks. For instance, it provides no current limiting and thus could be damaged if the output were shorted.

Next high-level section: FPGA Gateware

The operation of a voltage converter is more complicated than that of a voltage regulator. In this discussion we'll restrict ourselves to buck converters since that is what is used in the radar. That is, converters for which the output voltage is lower than the input voltage. However, the operation of boost converters and inverters is similar.

Figure 30 shows a possible implementation of a buck converter. This schematic has been adapted from AoE.

Ignore everything attached to the nMOS gate for the moment. We'll come back to it later. The salient point for now is that the transistor will be switched in a periodic way, with a percentage of that switching, $D$, (called the duty cycle) in the on state and the remaining percentage, $1-D$, in the off state.

We can describe this circuit with two different equations: one when the transistor is switched on and one when it is off.

In the on state,

And in the off state,

To simplify the analysis, Eq. (5.4.2.2b) approximates $V_{\mathrm{D}}$ as having 0 voltage drop. This is a reasonable approximation since the voltage drop across Schottky diodes is fairly small. If we were designing an actual switching converter we'd have to include this.

We can now impose the constraint

since otherwise the current would increase or decrease without bound. When we substitute in the current changes during the on and off states, we are left with following expression relating the input and output voltages:

Additionally, there are no lossy components here (aside from the small voltage drop between the nMOS drain and source) and so this device is theoretically 100% efficient. That is, $V_{\mathrm{in}}I_{\mathrm{in}}=V_{\mathrm{out}}I_{\mathrm{out}}$. The output capacitor will smooth the output $\Delta I_{\mathrm{on}}$, $\Delta I_{\mathrm{off}}$ ramp, and the average output voltage will be given by Eq. (5.4.2.4). Of course, real switching converters exhibit some loss, but the efficiency can often be upwards of 90%.

Before discussing the circuitry driving the transistor gate, it's worth addressing the Schottky diode which appears to play no role in the converter's function. Let's imagine what would happen if the diode were not present. When the transistor switches off, the inductor will go from seeing some current through it (call it $I_{0}$) to almost immediately seeing no current through it. The defining equation of an inductor is $V=LdI/dt$, so for very small $dt$ the inductor creates an enormous spike in the voltage across its leads trying to keep its current constant. This translates into the same huge spike at the nMOS source which is likely to damage the transistor. The presence of the Schottky provides a path for current to flow so that the voltage across the inductor peaks at one Schottky forward voltage drop.

Now we can move on to the gate driver circuitry. The oscillator block produces two signals: a clock pulse and a sawtooth ramp with the same period and phase as the clock pulse. This is shown graphically in Figure 31.

The error amplifier outputs a voltage proportional to the difference between the reference voltage and the divided output voltage. The flip flop in this circuit is a set-reset (SR) flip flop. So, the instant a high voltage arrives at its set input the output will go high, and the instant a high voltage arrives at its reset input the output will go low. The output voltage will remain as the last value it was set as until another high set or reset changes its output. For example, even though the clock pulse drops low immediately after being asserted, the output remains high until the reset pin is asserted. So, when the clock pulse arrives, the output will go high and remain that way until the sawtooth ramps to a voltage higher than the error voltage.

To understand this better imagine what happens when the output voltage is higher than its target set by the feedback loop. In this case, the error amplifier decreases its voltage and the duty cycle of the nMOS is reduced. We determined above that $V_{\mathrm{out}}=DV_{\mathrm{in}}$, so this has the effect of decreasing the output voltage. The opposite phenomenon occurs when the output voltage is below its target.